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SM8211M
NIPPON PRECISION CIRCUITS INC.
POCSAG Decoder For Pagers
OVERVIEW
The SM8211M is a POCSAG-standard (Post Office Code Standardization Advisory Group) signal processor LSI, which conforms to CCIR recommendation 584 concerning standard international wireless calling codes. The SM8211M supports call messages in either tone, numerical or character outputs at signal speeds of 512 bps or 1200 bps using a 76.8 kHz system clock, or 2400 bps using a double-speed 153.6 kHz system clock. Note that output timing values for 2400 bps mode operation are not shown in this datasheet, but can be obtained by halving the values for 1200 bps mode operation. CMOS structure and low-voltage operation realize low power dissipation, plus an intermittent-duty receive method (battery-saving function) reduces battery consumption. The SM8211M is available in 20-pin SSOPs.
s
s
s
s
Built-in input signal filter, with filter ON/OFF and 4 selectable filter characteristics 1.2 to 3.5 V (76.8 kHz system clock) or 2.0 to 3.5 V (153.6 kHz system clock) operating supply voltage Molybdenum-gate CMOS process realizes low power dissipation 20-pin SSOP
PINOUT
XVDD BS1 BS2 BS3 VDD TEST1 TEST2
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
XTN XT SYN-VAL RX-CLK ADD-DET VSS SIG-IN BACKUP RX-DATA RST
SM8211M
FEATURES
s s s s
TX-CLK TX-DATA BREAK
s
s
44 0.68 0.12
s
s
s s s
s
NIPPON PRECISION CIRCUITS--1
0.15 - 0.10
+ 0.05
0.30 0.15
1.80 0.05
0.60 0.15
s
Conforms to POCSAG standard for pagers 512 or 1200 bps signal speed Supports tone, numeric or character call messages Battery-saving function for low battery consumption BS1 (RF control main output signal) and BS3 (PLL setup signal) 60-step setup time setting--for BS3, 50.8 ms (max) at 1200 bps and 119.1 ms (max) at 512 bps Note that (BS3 setup time) - (BS1 setup time) should be set to 2. BS2 (RF DC-level adjustment signal) before/during reception selectable adjustment timing 6 addresses x 4 sub-addresses (total of 24 addresses) 1-bit and 2-bit burst error auto-correction function (messages only) 25 to 75% duty factor signal coverage (during preamble detection) 8 rate error detection condition settings 8 receive mode settings 76.8 or 153.6 kHz system clock (crystal oscillator or external clock input) Built-in oscillator capacitor
PACKAGE DIMENSIONS
7.40max 7.20 0.05 0.20 0.05
1.50
2.35
0.65 0.12
5.30 0.05 7.90 0.20
1.30 0.10
SM8211M
BLOCK DIAGRAM
RST
BACKUP
BREAK
BS1
BS2
BS3
XT Timing control XTN RX-CLK
TX-CLK
Flag register Address register
ADD-DET Data comparator SYN-VAL
TX-DATA
Receive data register
Preamble pattern Sync code Idle code
SIG-IN
Digital PLL
Error correction
RX-DATA
VDD XVDD VSS
TEST1
TEST2
PIN DESCRIPTION
Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 I:Input O:Output NIPPON PRECISION CIRCUITS--2 Name XVDD BS1 BS2 BS3 VDD TEST1 TEST2 TX-CLK TX-DATA BREAK RST RX-DATA BACKUP SIG-IN VSS ADD-DET RX-CLK SYN-VAL XT XTN I/O - O O O - I I I I I I O I I - O O O I O Description Oscillator circuit supply pin. Capacitor connected between XVDD and VSS. RF control main output signal RF DC-level adustment signal PLL setup signal Supply voltage Test pin. Leave open for normal operation. Test pin. Leave open for normal operation. ID data read sync clock ID data input Message transmission interrupt Hardware reset input Received data output (to CPU) Power save NRZ signal input pin Ground Address detection output. HIGH on detection Received data output sync clock Sync code detection output. HIGH on detection 76.8 or 153.6 kHz oscillator or external clock input pin Oscillator output pin
SM8211M
SPECIFICATIONS
Absolute Maximum Ratings
VSS = 0 V
Parameter Supply voltage range Input voltage range Power dissipation Storage temperature range Soldering temperature Soldering time Symbol VDD VIN PD Tstg Tsld tsld Rating -0.3 to 7.0 -0.3 to VDD + 0.3 250 -40 to 125 260 10 Unit V V mW C C s
Recommended Operating Conditions
VSS = 0 V
Parameter Supply voltage range Operating temperature range Symbol VDD Topr Condition 76.8 kHz system clock 153.6 kHz system clock Rating 1.2 to 3.5 V 2.0 to 3.5 -20 to 70 C Unit
DC Characteristics
VDD = 1.2 to 3.5 V, VSS = 0 V, Ta = -20 to 70 C unless otherwise noted
Rating Parameter Symbol Condition min XT = 76.8 kHz, VDD = 3.5 V XT = 153.6 kHz, VDD = 3.5 V - - 0.8VDD - IOH = -20 A, VDD = 2.0 V IOH = 20 A, VDD = 2.0 V VIN = VDD or VSS Ta = 25 C VDD - 0.1 - - - typ 20.0 25.0 - - - - - - max 30.0 A 35.0 - 0.2VDD - 0.1 1.0 1.0 V V V V A A Unit
Consumption
current1
IDD
HIGH-level input voltage (all inputs) LOW-level input voltage (all inputs) HIGH-level output voltage (all outputs except XTN) LOW-level output voltage (all outputs except XTN) Input leakage current (all inputs except XT) Standby supply current
VIH VIL VOH VOL IIL IDDS
1. The consumption current is slightly higher when RST is going LOW.
NIPPON PRECISION CIRCUITS--3
SM8211M
AC Characteristics
VDD = 1.2 to 3.5 V, VSS = 0 V, Ta = -20 to 70 C unless otherwise noted
Rating Parameter TX-CLK pulsewidth TX-CLK pulse cycle TX-DATA setup time TX-DATA hold time XT pulse frequency XT pulse duty cycle BREAK pulsewidth RX-CLK pulse cycle1 Symbol tPWTX tCYTX tSTX tHTX tCYXT DXT tPWBR 512 bps tCYRX 1200 bps 512 bps tPWRX 1200 bps 512 bps tSRX 1200 bps 512 bps tHRX 1200 bps Condition min 13 450 1.0 1.0 -250 ppm 25 13 - - - - - - - - typ - - - - 76.8 or 153.6 - - 1953 833 124 52 1341 573 488 208 max 100 - - - +250 ppm 75 - - - - - - - - - s s s s kHz % s s Unit
RX-CLK pulsewidth1
s
RX-DATA lead time1
s
RX-DATA hold time1
s
1. Internal digital PLL operation is subject to some change.
AC timing
t PWTX
t CYTX
TX-CLK
t STX
t HTX
TX-DATA
t CYRX
t PWRX
RX-CLK
t SRX
t HRX
RX-DATA
NIPPON PRECISION CIRCUITS--4
SM8211M
FUNCTIONAL DESCRIPTION
Receive Format
The receive format conforms to CCIR RPC No. 1 (POCSAG).
2nd and successive batches
Preamble
1st batch
SC
SC
Sync code word Continuous 576-bit "1,0" bit pattern Frame number 1 frame (= 2 code words)
... 1 0 1 0 1 0 1 0 1 0 ...
SC
0
1
2
3
4
5
6
7
1 code word (32 bits)
Figure 1. Receive signal format Sync signal (SC) The sync signal is a continuous code word in the received signal, used for word synchronization. It comprises 31 bits in an M-series bit pattern plus one
Table 1. Sync code word
Bit number 1 2 3 4 5 6 7 8 Bit value 0 1 1 1 1 1 0 0 Bit number 9 10 11 12 13 14 15 16 Bit value 1 1 0 1 0 0 1 0 Bit number 17 18 19 20 21 22 23 24 Bit value 0 0 0 1 0 1 0 1 Bit number 25 26 27 28 29 30 31 32 Bit value 1 1 0 1 1 0 0 0
even-parity bit, making a 32-bit signal. The sync code word pattern is shown in table 1.
NIPPON PRECISION CIRCUITS--5
SM8211M Code words (address and message signals) Each code word comprises 32 bits as shown in table 2.
Table 2. Code word format
Bit number Code word 1 (MSB)1 2 to 192 Function bits 20 0 Address signal 0 Address bits 0 1 1 Message signal 1 Message bits 21 0 1 0 1 Function A call B call C call D call Check bits Even-parity bit Check bits Even-parity bit 20, 212 22 to 313 32 (LSB)4
1. The MSB is the address/message code word control bit. It is 0 for an address signal, and 1 for a message signal. 2. Bits 2 to 21 contain the address or message information. 3. Bits 22 to 31 are BCH(31,21) format generated check bits, where BCH(n,k) = BCH(word length, number of information bits). 4. The LSB is an even-parity bit for bits 1 to 31.
Call number to call sign conversion This conversion expands a 7-digit decimal call number into a 21-bit binary call sign, as shown in figure 2. After expansion, the high-order 18 bits are assigned to bits 2 to 19 (address signal), and the low-order 3 bits are the user-defined frame identification pattern, which is stored in ID-ROM. The two function bits define which of four call functions is active.
7-digit decimal call signal (gap code)
1
2
3
4
5
6
7
MSB
LSB
21-bit binary conversion
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Frame identificaton pattern Call sign
1
Bits 2 to 19 (18 bits)
20
21
Bits 22 to 31 (10 bits)
32
Flag: 0 = address signal 1 = message signal
Function bits
BCH(31,21) generated check bits
Even-parity bit (for bits 1 to 31)
Figure 2. Call number to call sign conversion
NIPPON PRECISION CIRCUITS--6
SM8211M Idle signal (dummy signal) An idle word can be inserted into either the address or message signal to indicate that the word contains no information. The idle word bit pattern is shown in table 3. Message reception is halted when the receiver detects an idle word. In pager systems that send numeric data, the number of frames varies with the type of message being sent. In this case, an idle signal is transmitted to indicate completion of the message.
Table 3. Idle code word
Bit number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Bit value 0 1 1 1 1 0 1 0 1 0 0 0 1 0 0 1 Bit number 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Bit value
s
Battery Saving (BS1, BS2, BS3)
The SM8211M controls the intermittent-duty operation of the RF stage, which reduces battery consumption, and outputs three control signals (BS1, BS2, BS3). The function each signal controls in each mode is described below.
s
1 1 0 0 0 0 0 1 1 0 0 1 0 1 1 1
s
BS1 (RF-control main output signal)--The RF stage is active when BS1 is HIGH. The risingedge setup time for receive timing is set by flags RF0 to RF5 (60 steps). The maximum setup time is 49.167 ms at 1200 bps, and 115.234 ms at 512 bps. Note that 3C, 3D, 3E and 3F are invalid settings for BS1. BS2 (RF-control output signal)--BS2 is used to control the discharge of the receive signal DC-cut capacitor. The function of BS2 is determined by flag BS2, as described below. * When flag BS2 is 0, pin BS2 goes HIGH together with BS1 and then goes LOW again after the BS1 setup time. However, in lock mode (during address/message reception), it stays LOW. * When flag BS2 is 1, pin BS2 goes HIGH during lock mode sync code receive timing, and preamble mode and idle mode signal receive timing. BS3 (RF-control output signal)--BS3 is used to control PLL operation when the PLL is used. The rising-edge setup time for receive timing is set by flags PL0 to PL5 (60 steps). The maximum setup time is 50.833 ms at 1200 bps, and 119.141 ms at 512 bps. Note that 3E and 3F are invalid settings for BS3.
Note also that (BS3 rising-edge setup time) - (BS1 rising-edge setup time) should be 2.
Receive signal duty factor During preamble detection, the preamble pattern (1,0) is recognized at duty factors from 25% (min) to 75% (max) of the (1,0) preamble cycle.
NIPPON PRECISION CIRCUITS--7
SM8211M
Operating Modes
The SM8211M has four operating modes--SwitchON, Preamble, Idle and Lock modes. Note that all values in parentheses in the following figures are for the case when the speed is 1200 bps. Switch-ON mode After power is applied and after RST has gone LOW to reset all internal circuits, code words for the 27-bit flag data and the six 18-bit addresses are received from the CPU on TX-DATA and are stored. As each code word comprises 32 bits, this process takes (32 x 7) + 1 TX-CLK cycles to complete. When the 225 TX-CLK cycles have been received, BS1, BS2 and BS3 are set and device operation transfers to preamble mode.
RST
1 to 200 ms
X
TX-CLK 1 2 224 225
127 ms (54.2 ms)
TX-DATA
BS1
1.953 x N ms (0.833 x N ms)
BS2 (BS2 flag = 0)
BS2 (BS2 flag = 1) 1.953 x M ms (0.833 x M ms)
BS3
Preamble mode
X > 2 ms for external system clock operation or during continuous oscillations X > 900 ms for internal oscillator operation immediately after power is applied or BACKUP is released (VDD = 1.5 to 3.5 V) X > 1.5 s for internal oscillator operation immediately after power is applied or BACKUP is released (VDD < 1.5 V)
Figure 3. Switch-ON mode timing
NIPPON PRECISION CIRCUITS--8
SM8211M Preamble mode Preamble mode is a continuous 544-bit long period. If neither a preamble pattern, rate error nor sync code is detected during this period, operation transfers to idle mode. If a preamble pattern is detected, the preamble mode 544-bit long period is recommenced. If a rate error is detected, device operation transfers to idle mode. (A single error occurs when two active edges occur in the received signal on SIG-IN within 1-bit unit time. A rate error occurs when the number of errors in the error counter equals the error threshold set by flags ER0 to ER2. The error counter is reset when a preamble pattern is detected.) If the sync code is detected, SYN-VAL goes HIGH and operation transfers to lock mode. (If an error of 2 bits or less occurs, the detected word is recognized as the sync code.) Idle mode In idle mode, a check is made for the presence of a preamble signal when the RF intermittent-duty control signals (BS1, BS2, BS3) for battery saving are active. If a preamble pattern is detected, operation immediately transfers to preamble mode. If a preamble pattern is not detected, intermittent-duty operation continues. A preamble pattern is detected when either a 101010 or 010101 6-bit pattern is detected. Since there is a reasonable probability that this simple pattern can occur during a valid communicated signal (data, not preamble), this 6-bit pattern makes returning to preamble mode easier. This is useful for cases where weak electric fields, noise or other temporary interference cause device operation to transfer to idle mode. Further, if a sync code is detected within one cycle after device operation has transferred from lock mode, device operation returns to lock mode. (If flag BS2 is 0, pin BS2 does not go HIGH during the cycle after device operation has transferred from lock mode.)
BS1 62.5 ms (26.7 ms) Receive timing
1062.5 ms (453.3 ms)
BS2 (BS2 flag = 0) 1.953 x N ms (0.833 x N ms)
BS2 (BS2 flag = 1) 1.953 x M ms (0.833 x M ms)
BS3
Figure 4. Idle mode timing
Error bit
Preamble signal ... 1 0 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ... Preamble count starts Counting Preamble count restarts Preamble detected Count reset to 0
X
Figure 5. Preamble pattern sequence
NIPPON PRECISION CIRCUITS--9
SM8211M Lock mode If the sync code is detected during the preamble period, device operation transfers to lock mode and BS1 goes LOW. BS1 then goes HIGH again under frame timing, where the frame number is set by flags FF0 to FF2, and the 24 addresses are compared with ID-ROM (If the frame number is 0, BS1 stays HIGH). If errors of 2 bits or less occur, the address is still recognized. Since there are two code words per frame, this check is done twice. When one of the 24 addresses does not match, BS1 goes LOW and the device waits for the next sync code receive timing. If the sync code is still not detected after two consecutive attempts, device operation transfers to idle mode, except during message reception where operation stays in lock mode. If the sync code is not detected on the second attempt, but instead a pattern forming a preamble is detected, device operation transfers to preamble mode and not idle mode (preamble mode is more advantageous for sync code detection). When one of the 24 addresses does match, ADDDET goes HIGH for the duration of the next code word period and the corresponding 5-bit address information is transmitted to the CPU on RX-DATA in sync with RX-CLK. When the address information is confirmed, BS1 is held HIGH and the message is received. The 20-bit error-corrected message data, a 2-bit error correction result code and an evenparity bit form a 23-bit word that is sent to the CPU on RX-DATA in sync with RX-CLK. When an incoming message spans two or more batches, additional sync code detection occurs during sync code receive timing. Message reception ends when an address code or idle code is detected, or when interrupted using the BREAK input. When message reception ends, BS1 goes LOW and the device waits for either the address detect timing of the next frame or the sync code receive timing.
Switch-ON mode
A A: B: C: D: After RST goes LOW, ID code is read in sync with TX-CLK Rate error or, within a fixed period, preamble pattern or sync code not detected Preamble pattern detected Sync code detected 1 cycle immediately after transferring from lock mode
Preamble mode
E: Sync code not detected on 2 consecutive attempts F: Same as E, but preamble pattern detected on the second attempt G: Sync code detected G
B C D F
Idle mode
E
Lock mode
Figure 6. Operating mode transition diagram
NIPPON PRECISION CIRCUITS--10
Receive code
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SYN ICW ICW ADD MES MES ICW ADD MES MES MES MES ICW ICW ICW ADD MES SYN MES MES MES MES ICW ICW ADD MES MES MES MES ICW ADD MES ADD MES SYN
BS1
Address does not match
SYN-VAL 1.953 x N ms at 512 bps 0.833 x N ms at 1200 bps 1.953 x N ms at 512 bps 0.833 x N ms at 1200 bps
BREAK
ADD-DET
BS2 (flag BS2 = 1)
BS3 1.953 x M ms at 512 bps 0.833 x M ms at 1200 bps
1 2 3 4 5 6 7 0 1 2
SM8211M
1.953 x M ms at 512 bps 0.833 x M ms at 1200 bps
3 4 5 6 7
Receive code
0
SYN MES MES ICW ICW ICW ICW ADD MES MES MES MES MES MES MES MES MES SYN MES MES MES ICW ADD MES MES MES MES ICW ADD MES MES ICW ICW ICW SYN
BS1
Figure 7. Lock mode timing (frame ID number 3)
BREAK time BREAK detection to data halt delay time (2 bits max)
SYN-VAL
BREAK
ADD-DET
BS2 (flag BS2 = 1)
NIPPON PRECISION CIRCUITS--11
BS3
SM8211M
Address/Flag Data Transmission (CPU to SM8211M)
After device reset initialization, the address and flag data is transmitted from the CPU on TX-DATA in 225 cycles in sync with the falling edge of TX-CLK. (See the description in "Switch-ON mode"). The SM8211M supports six independent addresses (identified as A, B, C, D, E and F). Using these, it is possible to cover all kinds of group calls. The address data for each of the six addresses comprises an 18-bit address plus two function bits used to select one of four sub-addresses. Then, one MSB bit (0 for address signals), ten BCH(31,21) format generated check bits and an even-parity bit are added
Table 4. Address/flag transmit format
TX Data TX Data TX Data TX Data TX Data TX Data TX Data TX Data TX Data clock bit clock bit clock bit clock bit clock bit clock bit clock bit clock bit clock bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 0 SS S1 S0 LBO FF2 FF1 FF0 INV BS2 0 0 0 PL5 PL4 PL3 PL2 PL1 PL0 RF5 RF4 RF3 RF2 RF1 RF0 FL2 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 FL1 FL0 ER2 ER1 ER0 0 AA17 AA16 AA15 AA14 AA13 AA12 AA11 AA10 AA9 AA8 AA7 AA6 AA5 AA4 AA3 AA2 AA1 AA0 0 0 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 0 0 0 0 0 0 0 0 0 0 0 0 AB17 AB16 AB15 AB14 AB13 AB12 AB11 AB10 AB9 AB8 AB7 AB6 AB5 AB4 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 AB3 AB2 AB1 AB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 AC9 AC8 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 131 AD15 157 132 AD14 158 133 AD13 159 134 AD12 160 135 AD11 161 136 AD10 162 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 0 0 0 0 0 0 0 0 0 0 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 0 0 0 0 AE17 AE16 AE15 AE14 AE13 AE12 AE11 AE10 AE9 AE8 AE7 AE6 AE5 AE4 AE3 AE2 AE1 AE0 0 0 0 0 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 0 0 0 0 0 0 0 0 0 0 AF17 AF16 AF15 AF14 AF13 AF12 AF11 AF10 AF9 AF8 AF7 AF6 AF5 AF4 AF3 AF2 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 AF1 AF0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
to form 32-bit code words representing the address information which is then stored in RAM. This address information is then compared with the received data to determine correct addressing. If the number of addresses used is less than six, the same address should be repeated as many times as necessary to cancel the remaining addresses. Also, each 18-bit address should be input MSB first. The TX-CLK cycle and corresponding address data bits are shown in table 4, and the function of each flag is shown in tables 5 to 13.
AC17 123 AC16 124 AC15 125
100 AC14 126 101 AC13 127 102 AC12 128
103 AC11 129 AD17 155 104 AC10 130 AD16 156
NIPPON PRECISION CIRCUITS--12
SM8211M
Table 5. Flag functions
Flag SS S0, S1 LBO FF0 to FF2 INV BS2 PL0 to PL5 RF0 to RF5 FL2 FL0, FL1 ER0 to ER2 Function Receive mode set ON/OFF. ON when 1. One of eight operating conditions select (with LBO when SS is 1) 512/1200 bps speed select. 512 bps when 1. Frame number select Signal input (SIG-IN) normal/inverse select. Normal when 0. BS2 output signal mode select BS3 output signal rising-edge setup time for receive timing BS1 output signal rising-edge setup time for receive timing Internal digital filter ON/OFF. ON when 1. Digital filter parameter select (when FL2 is 1) Rate error detection threshold select
Table 6. Receive mode set flags1
Set flags SS 1 1 1 1 1 1 1 1 0 0 S1 0 0 1 1 0 0 1 1 x x S0 LBO PL5 PL4 PL3 PL2 PL1 PL0 RF5 RF4 RF3 RF2 RF1 RF0 FL2 FL1 FL0 ER2 ER1 ER0 0 1 0 1 0 1 0 1 x x 0 0 0 0 1 1 1 1 0 All other combinations not set automatically 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 0 1 1 1 1 1 0 1 0 0 0 1 1 0 0 0 1 0 1 0 1 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
1. x = don't care
Table 7. Baud rate flag
LBO 0 1 Baud rate 1200 bps 512 bps
Table 9. BS2 flag
BS2 0 1 BS2 operating mode See the description in section "Battery Saving (BS1, BS2, BS3)"
Table 8. Input polarity flag
INV 0 1 Polarity Normal Inverse
NIPPON PRECISION CIRCUITS--13
SM8211M
Table 10. Frame number flags
FF2 0 0 0 0 1 1 1 1 FF1 0 0 1 1 0 0 1 1 FF0 0 1 0 1 0 1 0 1 Frame number 0 1 2 3 4 5 6 7
Table 13. Rate error detection set flags
ER2 0 0 0 0 1 1 1 1 ER1 0 0 1 1 0 0 1 1 ER0 0 1 0 1 0 1 0 1 Rate error threshold Count = 1 Count = 2 Count = 3 Count = 4 Count = 5 Count = 6 Count = 7 Count = 8
Table 11. PLL setup time flags/BS1 rising-edge setup time flags1
PLL setup time (BS1 rising-edge setup time) LBO = 0 LBO = 1
PL5 PL4 PL3 PL2 PL1 PL0 (RF5) (RF4) (RF3) (RF2) (RF1) (RF0)
0 0 0 0 1 1 1
0 0 0 1 0 0 1
0 0 0 1 0 0 1
0 0 0 1 0 0 1
0 0 1 1 0 0 0
0 1 0 1 0 1 1
0.000 ms 0.833 ms 1.667 ms 25.833 ms 26.667 ms 27.500 ms
0.000 ms 1.953 ms 3.906 ms 60.547 ms 62.500 ms 64.453 ms
50.833 ms 119.141 ms
1. Note that (BS3 rising-edge setup time) - (BS1 rising-edge setup time) should be 2.
Table 12. Digital filter constant set flags1
FL2 0 1 1 1 1 1. x = don't care FL1 x 0 0 1 1 FL0 x 0 1 0 1 Filter constant Digital filter not used Filter constant 1 Filter constant 2 Filter constant 3 Filter constant 4
NIPPON PRECISION CIRCUITS--14
SM8211M
Received Data Transmission (SM8211M to CPU)
In lock mode, if the receive data for the frame is recognized as one of the 24 addresses with 2 bit errors or less, then ADD-DET goes HIGH for the duration of the next code word period and the corresponding 5-bit address information is transmitted to the CPU on RX-DATA in sync with RX-CLK.
Detected address codeword Internal bit clock
27 28 29 30 31 0 1 2 3 4 5 6 7 8 9
1 codeword
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
1
RX-CLK
RX-DATA
A0 A1 A2 A3 A4
ADD-DET
Figure 8. Received address transmit timing
Table 14. Address set flags
A0 0 1 0 1 0 1 0 1 0 1 0 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 A2 1 1 1 1 0 0 0 0 1 1 1 1 A3 0 0 0 0 1 1 1 1 1 1 1 1 A4 0 0 A 0 0 0 0 B 0 0 0 0 C 0 0 C call D call 0 1 1 1 0 0 1 1 1 1 C call D call A call B call 0 1 0 1 1 1 0 0 1 1 0 0 0 0 1 1 1 1 1 1 F C call D call C call D call A call B call 0 1 0 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 1 E C call D call A call B call Address Function A call B call A0 0 1 A1 0 0 A2 0 0 A3 0 0 A4 1 1 D C call D call A call B call Address Function A call B call
NIPPON PRECISION CIRCUITS--15
SM8211M When an address is detected, the next 32-bit data code word is received. The BCH(31,21) format error check bits are checked and if a 1-bit or two consecutive bit errors occur, they are corrected. Two random bit errors, or three or more bit errors are not corrected. If the corrected data MSB is 1, the data is recognized as a message, data reception continues and the corrected message data and error check flags are sent to the CPU. If the MSB is 0, the data is recognized as an address signal or idle code and data reception or data transmission to the CPU is halted.
Received message codeword Internal bit clock
27 28 29 30 31 0 1 2 3 4 5 6 7 8 9
1 codeword
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
1
RX-CLK 20-bit error-corrected message data
RX-DATA
E0 E1 PE
Figure 9. Received message transmit timing
Table 15. Error count flags
E0 0 1 0 1 E1 0 0 1 1 No errors 1-bit error Two consecutive bit errors Two random, or three or more bit errors Error count
Table 16. Parity check flag
PE 0 1 Even-parity check result1 No errors An error occurred
1. The even-parity check is performed on the data before error correction.
CPU Interface
SYN-VAL If a sync code is detected with two bit errors or less during sync code detection timing while in preamble, lock or idle mode, SYN-VAL goes HIGH for the duration of the next batch (544 bits long). ADD-DET If frame data is received and recognized with two bit errors or less while in lock mode, ADD-DET goes HIGH for the duration of the next code word period. If an address is detected in the second code word in the frame, ADD-DET stays HIGH for the duration of two code word periods. BREAK On a rising edge of BREAK, message reception and received message transmission are halted. After a BREAK interrupt, the device waits for frame address detection or sync code detection timing. This function is useful in cases of continuing message reception, because without sync code or other detection taking place the received data would be deemed to have many errors.
NIPPON PRECISION CIRCUITS--16
SM8211M
Extended Reset
When RST goes LOW for 1 to 2 ms or longer, BS1 and BS3 together go HIGH. Approximately 1 to 2 ms after RST goes HIGH, device operation continues. This function is useful for checking the RF stage circuits. After RST goes HIGH, the device waits for the ID code input.
When RST is LOW for less than 200 ms
RST
1 to 2 ms
1 to 2 ms
BS1
BS3
Figure 10. Extended reset timing
When RST is LOW for more than 200 ms
If the RST LOW-level pulsewidth exceeds 200 ms, the parameters for switch-ON mode should be quickly set over again as soon as RST returns HIGH.
> 200 ms 1 to 200 ms
RST
TX-CLK
TX-DATA
DATA
BS1
BS3
BS3 can also follow the dashed line during this interval.
Figure 11. Extended reset timing ( 200 ms) For internal oscillator operation, RST goes LOW for 1 ms or longer immediately after power is applied or just after a BACKUP release. After RST returns HIGH, a wait time of approximately 900 ms (VDD = 1.5 to 3.5 V) or 1.5 s (VDD < 1.5 V) should be observed before operation starts.
NIPPON PRECISION CIRCUITS--17
SM8211M
Power Save Control
When BACKUP goes LOW, the internal operation stops and all outputs go high impedance. When power save mode is released for normal operation, switch-ON mode internal initialization and ID code re-setting is required. The XT clock and TX-CLK timing when BACKUP goes LOW is described below. TX-DATA loading During TX-DATA loading, TX-CLK should be maintained and not stopped until the ID code is read in. Also, the XT clock should be maintained until after the equivalent time of 1 bit after the ID code is read in (150 cycles at 512 bps and 64 cycles at 1200 bps).
RST
XT
TX-CLK
BACKUP
1 bit equivalent time
BACKUP ENABLE (internal)
Figure 12. TX-DATA load timing TX-DATA when not loading After BACKUP has gone LOW, the XT clock should be maintained for the equivalent time of 65 bits or longer.
System Clock
The SM8211M operates using a 76.8 or 153.6 kHz system clock. The clock can be set up using a crystal oscillator or an externally input clock. For crystal oscillator clocks, only a crystal needs to be connected between XT and XTN. The oscillator amplifier, feedback resistor and oscillator capacitor are all built-in. For externally input clocks, the clock is connected to XT through a 100 pF to 0.1 F coupling capacitor. In both cases, crystal oscillator and external clock, a supply decoupling capacitor of 1000 pF to 0.1 F should be connected between XVDD and VSS. Also, the output on XTN should not be used as a clock to drive an external device.
Input Signal Digital Processing (Digital Filter)
In pagers, two baud rates, 512 and 1200 bps, are in use. The current method of ensuring the most suitable reception conditions is to substitute RF-stage LPF constants that are proportional to the baud rate. In the SM8211M, digital processing of the signal input deals with both baud rates without substituting RF-stage LPF constants. With this digital processing, a particularly small rise in the rate error probability can be expected. The digital processing can be set ON or OFF using flag FL2, and when ON, there are four filter constant settings that can be set using flags FL0 and FL1 to obtain the most suitable reception conditions in a flexible manner. (See table 12.)
NIPPON PRECISION CIRCUITS--18
SM8211M
FLOWCHARTS
Switch ON
Preamble
Idle
No RST = LOW Yes BS1 = BS3 = LOW Bit clock counter reset (T = 0) BS3 output timing Yes BS3 = HIGH
No
Bit clock count increment (T = T + 1)
No RST = HIGH Yes Preamble pattern
BS1 = BS2 = HIGH (BS1 = HIGH) Yes
No Yes Sync code detected Yes No Yes Rate error
BS2 = LOW (BS2 = HIGH)
BS1 = BS3 = LOW TX-CLK count reset (T = 0)
Just transferred from lock mode No
TX-CLK increment (T = T + 1) ID code and flags read in No Preamble present No No T = 225 No Yes BS1 = BS3 = LOW (BS1 = BS2 = BS3 = LOW) Receive timing finished T = 544 No Yes
ID code and flags set
Yes BS1 = BS3 = LOW (BS1 = BS2 = BS3 = LOW)
BS3 = HIGH
BS1 = BS2 = HIGH (BS1 = HIGH) No Sync code detected BS2 = LOW (BS2 = HIGH)
Yes
SYN-VAL = HIGH
Preamble
Idle
Lock
Preamble
Parentheses indicate operation with flag BS2 = 1.
NIPPON PRECISION CIRCUITS--19
SM8211M
Lock Message receive flag = 0
A
Yes Frame = 0 Sync code timing No
BS1 = BS3 = LOW (BS1 = BS2 = BS3 = LOW)
BS2 = LOW
BS1 = BS3 = LOW
Frame timing < frame
Frame timing = frame
BS1 = HIGH, BS3 = HIGH setup times for frames
B
No Address detected
Yes Frame = 7 Message receive flag = 1 No
Yes
ADD-DET = HIGH address information transmit
BS1 = BS3 = LOW
Yes Sync code timing
BS1 = HIGH, BS3 = HIGH setup times for sync code timing
No C (BS2 = HIGH) Yes Frame timing No Address Message/Address E
Message
Message Message/Address
Address Message transmit No Valid address
Yes
NIPPON PRECISION CIRCUITS--20
SM8211M
BREAK input
Message receive flag = 0 and message halts within 2 bits of time
Frame timing = frame No
Yes B
Wait until next code word
D
E
No Sync code detected
Yes No SYN-VAL = HIGH SYN-VAL = HIGH Yes Yes SYN-VAL = LOW Preamble present
No
1 Message receive flag 1 Message receive flag
0
0 BS1 = BS3 = LOW (BS1 = BS2 = BS3 =LOW)
A
C
Idle
Preamble
NIPPON PRECISION CIRCUITS--21
SM8211M
TYPICAL APPLICATIONS
Paging Receiver System
RF stage
Decoder
Alert
RF
Waveform generator
SM8211M decoder IC
Amplifier
SP
CPU
ID-ROM
D/D converter
LCD driver
LCD
Supply
Display
NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9402DE 1995.04
NIPPON PRECISION CIRCUITS INC.
NIPPON PRECISION CIRCUITS--22

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